1. Field of the System
The present system relates to field programmable gate array (FPGA) devices. More specifically, the system relates to a routing architecture between logic modules in an FPGA having segmented tracks that can be stepped and repeated such that the segment block only has to be designed once.
2. Background
FPGAs are known in the art. An FPGA comprises any number of logic modules, an interconnect routing architecture and programmable elements that may be programmed to selectively interconnect the logic modules to one another and to define the functions of the logic modules. An FPGA is an array of uncommitted gates with uncommitted wiring channels. To implement a particular circuit function, the circuit is mapped into an array and the wiring channels' appropriate connections are programmed to implement the necessary wiring connections that form the user circuit.
A field programmable gate array circuit can be programmed to implement virtually any set of functions. Input signals are processed by the programmed circuit to produce the desired set of outputs. Such inputs flow from a user's system, through input buffers and through the circuit, and finally back out the user's system via output buffers.
An FPGA core tile may be employed as a stand-alone FPGA, repeated in a rectangular array of core tiles, or included with other devices in a system-on-a-chip (SOC). The core FPGA tile may include an array of logic modules and input/output modules. An FPGA core tile may also include other components such as read only memory (ROM) modules. Horizontal and vertical routing channels provide interconnections between the various components within an FPGA core tile. Programmable connections are provided by programmable elements between the routing resources.
The programmable elements in an FPGA can be either one-time programmable or re-programmable. Re-programmable elements used in FPGA technologies may comprise transistors or other re-programmable elements as is well known to those of ordinary skill in the art. One-time programmable elements used in FPGA technologies may comprise antifuse devices.
Horizontal and vertical routing channels are comprised of a varying number of routing tracks. It is often desirable to segment routing tracks. Segmented routing tracks increase the speed and performance of integrated circuits. For instance, if a particular integrated circuit has long routing tracks due to the size of the device, the time it takes for a signal to travel along the routing tracks may be long due to increased resistance and capacitive loading on the tracks. This is especially true in antifuse FPGAs. Unprogrammed antifuses along the routing tracks act as small capacitors, and thus decrease the performance and speed in antifuse FPGAs. Segmented tracks also reduce die area. Using an entire routing track to route a signal when only a portion of the track is required tends to waste die area.
It is even more desirable if the segmentation of the routing tracks is non-uniform. A non-uniform segmented channel array provides a variety of track lengths, and thus is more flexible and faster than a device having a uniform segmented channel array. Segmented tracks also reduce die area. For example, in a non-uniform segmented channel array, if a signal has to travel a track distance comprising a certain predetermined track length, it is more likely that that track length can be closely matched in a non-uniform segmented channel array due to the variety of track lengths and combinations of track lengths to choose from.
The problems associated with non-uniform segmented channel array architecture arise from a design and verification viewpoint. As is well known to those skilled in the art of integrated circuit design, non-uniform channel array architectures do not lend themselves to modular design. Modular design of integrated circuits involves the designing one portion of the circuit as a small block. The small block is then stepped and repeated across the entire chip. This procedure is known in the art as tiling.
Non-uniform segmented channel array architectures do not lend themselves to modular design due to the unique nature of each non-uniform track segment. Because of this various problems arise when designing a non-uniform segmented channel array. For example, the circuit design of each channel has to be drawn manually for the entire length of the chip. The same circuit design has to be repeated in the software device description. In addition, arrays with non-uniform segmented channels in two dimensions (i.e. horizontal and vertical) have a unique circuit design at each intersection of a horizontal channel and vertical channel in the array. Thus, the mask design and layout has to be repeated for every unique intersection of channels, the number of which tends to grow as the product of the number of channels in each direction grows.
Further, non-uniform segmented channel array architectures greatly increase the complexity of the verification problem. For example, the effort required to verify the circuit design against the architecture, the mask design against the circuit design, the software design against the architecture, etc., is proportional to the number of channel intersections in the array. Manual inspection of each channel track addressing signal and programmable element locations is already error prone and is amplified in the case of non-uniform segmented channel array architectures due to having to check the entire circuit rather than a block that has been repeated throughout the circuit.
Thus, there is a need in the art for a non-uniform segmented channel array architecture that can be designed as a block that may be stepped and repeated to build an entire chip. There is also a need in the art for a non-uniform segmented channel array block, i.e. circuit design, mask design, layout and software device description, that need be designed only once.